All magnetic memory arrays are provided with magnetic shields to exclude any influence from external magnetic fields. In practice, however, no continuous shield layer can be 100% perfect and even adding additional continuous shielding layers would not help to avoid the degradation of MRAM operational margin due to external stray magnetic fields.
This is especially true for a segmented bit line scheme, an example of which is shown in FIG. 1. Seen there is an array of magnetic memory elements such as element 11 which is a MTJ (magnetic tunnel junction) or a GMR (giant magneto resistance) device.
Passing vertically (in the figure) across each memory element is a single bit line which intersects a horizontal word line so that a given element is addressed only when both these lines are simultaneously activated. In the segmented design shown here, the bit lines are segmented into groups, or bit slices, such as 12, and additional select lines are provided so that only the word lines within a given bit slice are powered up at any given time.
MRAMs using MTJs are strong candidate to provide a dense (areas of 8-25f2, where f is the smallest feature size), fast (1-30 ns read/write speed), and non-volatile storage solution for future memory applications. The MTJ utilizes at least 2 magnetic layers, that sandwich a thin dielectric layer such as Al2O3, AlNxOy, or MgO with one magnetic layer being pinned by an antiferromagnetic film. To protect data from being erased or from thermal agitation, an in-plane uniaxial magnetic anisotropy is needed for the magnetic free layer to store data.
The cross point of Word Line and Bit Line currents programs the MTJs of the MRAM cells. The problem of the cells along the same word line and bit lines being disturbed is a major concern. The Segmented Word Line arrangement, as described in reference (1) below, eliminated disturb conditions of cells on the same word line outside the selected segment. When the operating point is chosen deep along the hard axis, the required bi-directional bit line currents to program the selected cells are significantly reduced. The possibility of disturbance along the bit line is also reduced. This represents an ideal MRAM operating condition.
The switching fields generated by word line and bit line currents for the conventional MRAM are about 20-50 Oe in intensity. For the segmented word line scheme, the bias field generated by the write word line is about 30-50 Oe while the switching field generated by a bit line is about 10 Oe. Magnetic fields of higher intensity are often encountered in everyday life. For example, magnetic fields generated by telephone receivers. Furthermore, if MRAMs are manufactured using a conventional package approach, the problem also occurs. Due to the increase in density in packaging techniques, in an environment in which the MRAM is actually used, power lines or the like may have to pass by elements. Then, possible leakage magnetic fields may destroy stored data.
Accordingly, measures must be taken to protect the MRAM from these stray magnetic fields. Typically, as seen in cross-section in FIG. 2, the MRAM array will be covered by permeable layer 21, such as a thick NiFe layer. This magnetic soft layer reduces the effects of stray magnetic fields on the MRAM. But this may not provide perfect shielding. First, magnetic domains are very difficult to arrange/control in order to shield MRAMs from external stray fields in both hard axis and easy axis directions. Second, magnetic domains and domain walls in the shielding magnetic soft layer could generate additional small stray field on its covered MRAM cells.
These problems are different for the segmented word line scheme: In the hard axis direction, the biasing field generated by a write word line is large and therefore can tolerate small stray field without affecting writing margin; but in the easy axis direction, the switching field generated by a bit line is very small and easily interrupted by small stray fields, thereby reducing the MTJ free layer switching margin.
Alternatively, different magnetic shield measures have been proposed which are carried out during the packaging step utilizing a powdered magnetic substance (3,4). However, these arrangements tend to complicate the packaging technique and may also generate unwanted non-uniform stray fields on the MRAM. A different approach to dealing with the approach is disclosed as part of the present invention.
A routine search of the prior art was performed with the following additional references of interest being found:
In U.S. Pat. No. 6,335,890, (Roehr et al. disclose global and local word lines where the global word lines are isolated from the memory cells, write lines and bit lines orthogonal, and a switch for each word line segment. In U.S. Pat. No. 6,429,044, Tuttle describes a shield partially or completely surrounding an integrated circuit. There may be multiple shields or overlapping shields.
U.S. Pat. No. 6,867,468 (Sharma et al.) shows a magnetic shield above and below the bit plane. The magnetic shield may be patterned. U.S. Patent Application 2004/0126905 (Bhattacharyya et al.) teaches a metal shield over each layer of memory cells or over all memory cells.
Fukuzumi discloses a magnetic shield surrounding a magnetic element in U.S. Patent Application 2004/0232536. Min et al., show a shield to fit each MTJ cell in U.S. Patent Application 2005/0059170 (made to a common assignee as the present invention).